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fremont micro devices FT24C512A ? 2009 fremont micro devices inc. ds3009e-p age 1 two-wire serial eeprom 512k (8-bit wide) features ? low voltage and low power operations: ? FT24C512A: v cc = 1.8v to 5.5v ? maximum standby current < 1a (typically 0.02 a and 0.06a @ 1.8v and 5.5v respectively). ? 128 bytes page write mode. ? partial page write operation allowed. ? internally organized: 65,536 8 (512k). ? standard 2-wire bi-directional serial interface. ? schmitt trigger, filtered inputs for noise protection. ? self-timed write cycle (5ms maximum). ? 1 mhz (5v), 400 khz (1.8v, 2.5v, 2.7v) compatibility. ? automatic erase before write operation. ? write protect pin for hardware data protection. ? high reliability: typically 1,000,000 cycles endurance. ? 100 years data retention. ? industrial temperature range (-40 o c to 85 o c). ? standard 8-pin dip/sop/wsop/m sop/tssop pb-free packages. description the FT24C512A series are 524,288 bits of serial electrical erasable and programmable read only memory, commonly known as eeprom. they are organiz ed as 65,536 words of 8 bi ts (one byte) each. the devices are fabricated with proprietary advan ced cmos process for low power and low voltage applications. these devices are available in standa rd 8-lead dip, 8-lead sop/wsop/msop and 8-lead tssop packages. a standard 2-wire serial interfac e is used to address all read and write functions. our extended vcc range (1.8v to 5.5v) devices enables wide spectrum of applications. pin configuration pin name pin function a2, a1, a0 device address inputs sda serial data input / open drain output scl serial clock input wp write protect nc no-connect table 1
FT24C512A all three packaging types come in pb-free certified. vcc wp scl sda a2 a1 a0 gnd FT24C512A 1 2 3 4 8 7 6 5 8l sop 8l tssop 8l dip 8l wsop 8l msop figure 1: package type absolute maximum ratings industrial operating temperature: -40 o c to 85 o c storage temperature: -50 o c to 125 o c input voltage on any pin relative to ground: -0.3v to v cc + 0.3v maximum voltage: 8v esd protection on all pins: >2000v * stresses exceed those listed under ?absolute maximum rating? may cause permanent damage to the device. functional operation of the device at conditions beyond those listed in the specification is not guaranteed. prolonged exposure to extreme conditions may affect device reliability or functionality . figure 2: block diagram ds3009e-page 2 ? 2009 fremont micro devices inc.
FT24C512A pin descriptions (a) serial clock (scl) the rising edge of this scl input is to latch data into the eeprom device while the falling edge of this clock is to clock data out of the eeprom device. (b) device / chip select addresses (a2, a1, a0) these are the chip select input signals for the serial eeprom devices. typically, these signals are hardwired to either v ih or v il . if left unconnected, they are internally recognized as v il . (c) serial data line (sda) sda data line is a bi-directional signal for the serial devices. it is an open drain output signal and can be wired-or with other open-drain output devices. (d) write protect (wp) the FT24C512A device has a wp pin to protec t the whole eeprom array from programming. programming operations are allowed if wp pi n is left un-connected or input to v il . conversely all programming functions are disabled if wp pin is connected to v ih or v cc . read operations is not affected by the wp pin?s input level. memory organization the FT24C512A devices have 512 pages respective ly. since each page has 128 bytes, random word addressing to FT24C512A will require 16 bits data word addresses. device operation (a) serial clock and data transitions the sda pin is typically pulled to high by an external resistor. data is allowed to change only when serial clock scl is at v il . any sda signal transition may interpret as either a start or stop condition as described below. (b) start condition with scl v ih , a sda transition from high to low is inte rpreted as a start condition. all valid commands must begin with a start condition. (c) stop condition with scl v ih , a sda transition from low to high is interpreted as a stop condition. all valid read or write commands end with a stop condition. the device goes into the standby mode if it is after a read command. a stop condition after page or byte write command will trigger the chip into the standby mode after the self-timed internal programming finish (see figure 3). ? 2009 fremont micro devices inc. ds30 09e-page 3
ft24c512/a ds3009e-page 4 ? 2009 fremont micro devices inc. (d) acknowledge the 2-wire protocol transmit s address and data to and from th e eeprom in 8 bit words. the eeprom acknowledges the data or address by outputting a "0" after receiving each word. the acknowledge signal occurs on the 9th serial clock after each word. (e) standby mode the eeprom goes into low power standby mode after a fresh power up, after receiving a stop bit in read mode, or after completing a self-time internal programming operation. figure 3: timing diagram for start and stop conditions figure 4: timing diagram for output acknowledge scl sda start condition stop condition data data valid transition scl data in data out start condition a ck
FT24C512A device addressing the 2-wire serial bus protocol mandates an 8 bits device address word after a start bit condition to invoke a valid read or write command. the first four most significant bits of the device address must be 1010, which is common to all serial eeprom devices. t he next three bits are devic e address bits. these three device address bits (5 th , 6 th and 7 th ) are to match with the external chip select/address pin states. if a match is made, the eeprom device outputs an acknowledge signal after the 8 th read/write bit, otherwise the chip will go into standby mode. however, matching may not be needed for some or all device address bits (5 th , 6 th and 7 th ) as noted below. the last or 8th bit is a read/write command bit. if the 8 th bit is at vih then the chip goes into read mode. if a ?0? is detected, the device enters programming mode. write operation (a) byte write a write operation requires two 8-bit data word address following the device address word and acknowledge signal. upon receipt of this addr ess, the eeprom will resp ond with a ?0? and then clock in the first 8-bit data word. following rece ipt of the 8-bit data word, the eeprom will again output a ?0?. the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. at this time the eeprom enters into an internally-timed write cycle state. all inputs are disabled during this write cycle a nd the eeprom will not resp ond until the writing is completed (figure 5). (b) page write the 512k eeprom are capable of 128-byte page write. a page write is initiated the same way as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. the microcontroller can transmit up to 127 more data words after the eeprom ac knowledges receipt of the first data word. the eeprom will respond with a ?0? after each data word is received. t he microcontroller must terminate the page write sequence with a stop condition (see figure 6). the lower 7 bits of the data word address are inter nally incremented following the receipt of each data word. the higher data word address bits are not incremented, retaining the memory page row location. if more than 128 data words are transmitted to the eeprom, the data word address will ?roll over? and the previous data will be overwritten. (c) acknowledge polling acknowledge polling may be used to poll the programming status during a self-timed internal programming. by issuing a valid read or writ e address command, the eepr om will not acknowledge at the 9 th clock cycle if the device is still in the se lf-timed programming mode. however, if the programming completes and the chip has returned to the standby mode, the device will return a valid acknowledge signal at the 9 th clock cycle. ? 2009 fremont micro devices inc. ds30 09e-page 5
ft24c512/a ds3009e-page 6 ? 2009 fremont micro devices inc. read operations the read command is similar to t he write command except the 8 th read/write bit in add ress word is set to ?1?. the three read operation modes are described as follows: (a) current address read the eeprom internal address word counter maintain s the last read or write address plus one if the power supply to the device has not been cut off. to initiate a current address read operation, the micro-controller issues a start bit and a valid device address word with the read/write bit (8 th ) set to ?1?. the eeprom will response with an acknowledge signal on the 9 th serial clock cycle. an 8- bit data word will then be serially clocked out. the internal address word counter will then automatically increase by one. for current addr ess read the micro-controller will not issue an acknowledge signal on the 18 th clock cycle. the micro-controller issues a valid stop bit after the 18 th clock cycle to terminate the read operation. the device then returns to standby mode (see figure 7). (b) sequential read the sequential read is very similar to current addres s read. the micro-controller issues a start bit and a valid device address word with read/write bit (8 th ) set to ?1?. the eeprom will response with an acknowledge signal on the 9 th serial clock cycle. an 8-bi t data word will then be serially clocked out. meanwhile the internally address word counter will then automatically increase by one. unlike current address read, the micro-controller sends an acknowledge signal on the 18th clock cycle signaling the eeprom device that it want s another byte of data. upon receiving the acknowledge signal, the eeprom will serially clocked out an 8-bit data word based on the incremented internal address counter. if the micr o-controller needs another data, it sends out an acknowledge signal on the 27 th clock cycle. another 8-bit data word will then be serially clocked out. this sequential read continues as long as the micro-controller sends an acknowledge signal after receiving a new data word. when the inte rnal address counter reaches its maximum valid address, it rolls over to the beginning of the memo ry array address. similar to current address read, the micro-controller can terminate the sequential read by not acknowledging the last data word received, but sending a stop bit afterwards instead (figure 8). (c) random read random read is a two-steps process. the first step is to initialize the internal address counter with a target read address using a ?dummy write? instruct ion. the second step is a current address read. to initialize the internal address counter with a target read address, the micro-controller issues a start bit first, follows by a valid device address with the read/write bit (8 th ) set to ?0?. the eeprom will then acknowledge. th e micro-controller will then send two address word s. again the eeprom will acknowledge. instea d of sending a valid written data to the eeprom, the micro-controller performs a current address read instruction to read t he data. note that once a start bit is issued, the eeprom will reset the internal programming pr ocess and continue to execute the new instruction - which is to read the current address (figure 9).
FT24C512A ? 2009 fremont micro devices inc. ds30 09e-page 7 sda line s t a r t m s b device address l s b r / w a c k w r i t e first word address m s b a c k a c k a c k l s b second word address s t o p data figure 5: byte write sda line s t a r t m s b device address l s b r / w a c k w r i t e first word address(n) m s b a c k a c k a c k l s b second word address(n) s t o p data(n) a c k data(n+x) ... figure 6: page write sda line s t a r t m s b device address l s b r / w a c k r e a d a c k n o a c k s t o p data figure 7: current address read sda line device address r / w a c k r e a d a c k n o a c k s t o p data (n) data (n+1) data (n+2) data (n+3) a c k a c k a c k figure 8: sequential read
ft24c512/a ds3009e-page 8 ? 2009 fremont micro devices inc. s t a r t m s b device address l s b r / w a c k r e a d a c k n o a c k s t o p data (n) s t a r t m s b device address l s b r / w a c k w r i t e first word address(n) m s b a c k l s b second word address(n) a c k sda line figure 9: random read low high t t t low t t f r t su.dat t hd.dat t hd.sta t su,sta t su.sto t t t dh buf aa scl sda in sda out figure 10: scl and sda bus timing
FT24C512A ac characteristics 1.8v 2.5-5.0 v symbol parameter min max min max unit f scl clock frequency, scl 400 1000 khz t low clock pulse width low 1.3 0.4 s t high clock pulse width high 0.6 0.4 s t i noise suppression time (1) 180 120 ns t aa clock low to data out valid 0.05 0.9 0.05 0.55 s t buf time the bus must be free before a new transmission can start (1) 1.3 0.5 s t hd.sta start hold time 0.6 0.25 s t su.sta start set-up time 0.6 0.25 s t hd.dat data in hold time 0 0 s t su.dat data in set-up time 100 100 ns t r input rise time (1) 0.3 0.3 s t f input fall time (1) 300 100 ns t su.sto stop set-up time 0.6 0.25 s t dh date out hold time 50 50 ns t wr write cycle time 5 5 ms endurance (1) 25 o c, page mode, 3.3v 1,000,000 write cycles notes: 1. this parameter is expected by characterization but are not fully screened by test. 2. ac measurement conditions: r l (connects to vcc): 1.3k ? input pulse voltages: 0.3vcc to 0.7vcc input and output timing reference voltages: 0.5vcc ? 2009 fremont micro devices inc. ds30 09e-page 9
ft24c512/a ds3009e-page 10 ? 2009 fremont micro devices inc. dc characteristics symbol parameter test conditions min typical max units v cc1 24c a supply v cc 1.8 5.5 v i cc supply read current v cc @ 5.0v scl = 100 khz 0.4 1.0 ma i cc supply write current v cc @ 5.0v scl = 100 khz 2.0 3.0 ma i sb1 supply current v cc @ 1.8v, v in = v cc or v ss 0.02 1.0 a i sb2 supply current v cc @ 2.5v, v in = v cc or v ss 1.0 a i sb3 supply current v cc @ 5.0v, v in = v cc or v ss 0.07 1.0 a i il input leakage current v in = v cc or v ss 3.0 a i lo output leakage current v in = v cc or v ss 3.0 a v il input low level -0.6 v cc 0.3 v v ih input high level v cc 0.7 v cc +0.5 v v ol2 output low level v cc @ 3.0v, i ol = 2.1 ma 0.4 v v ol1 output low level v cc @ 1.8v, i ol = 0.15 ma 0.4 v order code: ft24cxxa ? xxx - x temperature range package d: dip s: sop m: msop t: tssop option g: green package rohs compliant r: rohs compliant packaging b: tube t: tape and reel u: -40 to 85? w: wsop
FT24C512A order information order code vcc temperature range package option packaging FT24C512A-udr-b rohs tube FT24C512A-udg-b dip8 green package tube FT24C512A-usr-b rohs tube FT24C512A-usr-t rohs t/r FT24C512A-usg-b green package tube FT24C512A-usg-t sop8 green package t/r FT24C512A-uwr-b rohs tube FT24C512A-uwr-t rohs t/r FT24C512A-uwg-b green package tube FT24C512A-uwg-t wsop8 green package t/r FT24C512A-umr-b rohs tube FT24C512A-umr-t rohs t/r FT24C512A-umg-b green package tube FT24C512A-umg-t msop8 green package t/r FT24C512A-utr-b rohs tube FT24C512A-utr-t rohs t/r FT24C512A-utg-b green package tube FT24C512A-utg-t 1.8-5.5v -40-85 tssop8 green package t/r ? 2009 fremont micro devices inc. ds30 09e-page 11
ft24c512/a ds3009e-page 12 ? 2009 fremont micro devices inc. dip8 package outline dimensions dimensions in millimeters dimensions in inches symbol min max min max a 3.710 4.310 0.146 0.170 a1 0.510 0.020 a2 3.200 3.600 0.126 0.142 b 0.380 0.570 0.015 0.022 b1 1.524 bsc 0.060 bsc c 0.204 0.360 0.008 0.014 d 9.000 9.400 0.354 0.370 e 6.200 6.600 0.244 0.260 e1 7.320 7.920 0.288 0.312 e 2.540 (bsc) 0.100 bsc l 3.000 3.600 0.118 0.142 e2 8.400 9.000 0.331 0.354
FT24C512A sop8 package outline dimensions (150mil) dimensions in millimeters dimensions in inches symbol min max min max a 1.350 1.750 0.053 0.069 a1 0.100 0.250 0.004 0.010 a2 1.350 1.550 0.053 0.061 b 0.330 0.510 0.013 0.020 c 0.170 0.250 0.006 0.010 d 4.700 5.100 0.185 0.200 e 3.800 4.000 0.150 0.157 e1 5.800 6.200 0.228 0.244 e 1.270 (bsc) 0.050 bsc l 0.400 1.270 0.016 0.050 0 8 0 8 ? 2009 fremont micro devices inc. ds30 09e-page 13
ft24c512/a ds3009e-page 14 ? 2009 fremont micro devices inc. wsop8 package outline dimensions (208 mil) dimensions in millimeters dimensions in inches symbol min max min max a 1.750 2.160 0.069 0.085 a1 0.050 0.250 0.002 .0098 a2 1.700 1.900 0.067 0.075 b 0.355 0.480 0.014 0.019 c 0.190 0.240 0.0075 0.0095 d 5.130 5.330 0.202 0.210 e 5.130 5.330 0.202 0.210 e1 7.750 8.080 0.305 0.318 e 1.270 (bsc) 0.050 bsc l 0.510 0.760 0.02 0.03 0 8 0 8
FT24C512A tssop8 package outl ine dimensions dimensions in millimeters dimensions in inches symbol min max min max d 2.900 3.100 0.114 0.122 e 4.300 4.500 0.169 0.177 b 0.190 0.300 0.007 0.012 c 0.090 0.200 0.004 0.008 e1 6.250 6.550 0.246 0.258 a 1.100 0.043 a2 0.800 1.000 0.031 0.039 a1 0.020 0.150 0.001 0.006 e 0.65 (bsc) 0.026 (bsc) l 0.500 0.700 0.020 0.028 h 0.25 (typ) 0.01 (typ) 1 7 1 7 ? 2009 fremont micro devices inc. ds30 09e-page 15
ft24c512/a ds3009e-page 16 ? 2009 fremont micro devices inc. msop8 package outline dimensions dimensions in millimeters dimensions in inches symbol min max min max a 0.820 1.100 0.320 0.043 a1 0.020 0.150 0.001 0.006 a2 0.750 0.950 0.030 0.037 b 0.250 0.380 0.010 0.015 c 0.090 0.230 0.004 0.009 d 2.900 3.100 0.114 0.122 e 0.65 (bsc) 0.026 (bsc) e 2.900 3.100 0.114 0.122 e1 4.750 5.050 0.187 0.199 l 0.400 0.800 0.016 0.031
FT24C512A appendix a revision history version a: original data sheet for ft24c512/a. * information furnished is believed to be accurate and reliabl e. however, fremont micro devices, incorporated (bvi) assumes no responsibility for the consequences of use of su ch information or for any infringement of patents of other rights of third parties which may result from its us e. no license is granted by implication or otherwise under any patent rights of fremont micro devi ces, incorporated (bvi). specificatio ns mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. fremont micro devices, incorporated (bvi) products are not authorized for use as critical components in life support devices or systems without express written approval of frem ont micro devices, incorporat ed (bvi). the fmd logo is a registered trademark of fremont micro devices, incorporated (bvi). all ot her names are the property of their respective owners. ? 2009 fremont micro devices inc. ds30 09e-page 17

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